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1 for more information www.linear.com/ltc3853 typical application features description triple output, multiphase synchronous step-down controller the lt c ? 3853 is a high performance triple output step- down switching regulator controller that drives all n- channel synchronous power mosfet stages. power loss and supply noise are minimized by operating the output stages out of phase. the part can be configured as a dual phase controller plus a single phase controller if needed. the part can also be configured to provide a single 3-phase output for even higher output currents. a wide 4.5v to 24v (28v maximum) input voltage sup - ply range encompasses most battery chemistries and intermediate bus voltages. phase 3 can regulate output voltages up to 13.5v. a constant-frequency current mode architecture allows for a phase-lockable frequency up to 750khz. independent tk/ss pins for each output ramps the output voltages and can be configured for coincident or ratiometric tracking. current foldback limits mosfet heat dissipation during short- circuit conditions. the mode/pllin pin selects among burst mode ? operation, pulse-skipping or continuous inductor current modes. high efficiency triple 5v/3.3v/1.2v step-down converter n triple , 120 phased controllers reduce required input capacitance and power supply induced noise n configurable as a 180 dual phase controller plus a single phase controller n the third phase can regulate up to a 13.5v output n high efficiency: up to 92% n r sense or dcr current sensing n 0.75% 0.8v output voltage accuracy n phase-lockable fixed frequency 250khz to 750khz n supports pre-biased outputs n dual n-channel mosfet synchronous drive n wide v in range: 4.5v to 24v operation (28v abs max) n adjustable soft-start current ramping or tracking n foldback output current limiting n output overvoltage protection n dual power good output voltage monitors n 40-lead 6mm 6mm qfn package l, lt , lt c , lt m , linear technology, burst mode, polyphase and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. tg1 tg2 boost1,2,3 sw1 sw2 bg1 bg2 sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1,2,3 v in intv cc ltc3853 mode/pllin 20k freq/pllfltr i lim pgnd pgood12 sgnd tk/ss1,2,3 v fb3 sense3 ? sense3 + sw3 tg3 bg3 run1,2,3 pgood3 2.2k 15k 20k 63.4k 0.1f 4.7f 10k f in 500khz v out1 5v 5a v out2 3.3v 5a 20k 1k 2.2k v out3 1.2v 5a v in 7v to 24v 1500pf 100f 10v 220pf 10nf 22f 50v 0.1f 0.1f 2.2h 2.2h 1h 0.1f sw1,2,3 0.1f + 100f 6v + 100f 6v + 10k 105k ltc 3853 3853fc
2 for more information www.linear.com/ltc3853 absolute maximum ratings input supply voltage ( v in ) ......................... 28 v to C0.3 v topside driver voltages boost 1, boost 2, boost 3 .................. 34 v to C0.3 v switch voltage ( sw 1, sw 2, sw 3) ................ 28 v to C5 v intv cc , run 1, run 2, run 3, pgood 12, pgood 3, drv cc 12 , extv cc , ( boost 1- sw 1), ( boost 2- sw 2), ( boost 3- sw 3) ................. 6 v to C0. 3 v sense 1 + , sense 2 + , sense 1 C , sense 2 C voltages .................................... 5.7 v to C0. 3 v sense 3 + , sense 3 C .................................... 14 v to C0.3 v v fb 2 ....................................................... 300 a max i fb 2 mode / pllin , i lim , tk / ss 1, tk / ss 2, tk / ss 3 voltages ..................... intv cc to C0.3 v i th 1 , i th 2 , i th 3 , v fb 1 , v fb 3 voltages ...... intv cc to C0.3 v intv cc peak output current ................................ 150 ma operating junction temperature range ( note 3) e - grade , i - grade ................................ C40 c to 125 c h - grade ............................................. C40 c to 150 c mp - grade .......................................... C55 c to 150 c storage temperature range .................. C65 c to 150 c (note 1) 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 tk/ss2 tk/ss3 sense1 + sense1 ? sense2 + sense2 ? sense3 + sense3 ? v fb1 i th1 bg1 drv cc12 bg2 sw2 tg2 boost2 v in extv cc intv cc bg3 tk/ss1 i lim freq/pllfltr mode/pllin run1 run2 run3 boost1 tg1 sw1 sgnd v fb2 i th2 v fb3 i th3 pgood3 pgood12 boost3 tg3 sw3 21 30 10 1 uj package 40-lead (6mm 6mm) plastic qfn t jmax = 150c, ja = 33c/w exposed pad (pin 41) is pgnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc3853euj#pbf ltc3853euj#trpbf ltc3853uj 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3853iuj#pbf ltc3853iuj#trpbf ltc3853uj 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3853huj#pbf ltc3853huj#trpbf ltc3853uj 40-lead (6mm 6mm) plastic qfn C40c to 150c ltc3853mpuj#pbf ltc3853mpuj#trpbf ltc3853uj 40-lead (6mm 6mm) plastic qfn C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc 3853 3853fc
3 for more information www.linear.com/ltc3853 electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 3), v in = 15v, v run1,2,3 = 5v, unless otherwise noted. symbol parameter conditions min typ max units main control loops output voltage range channels 1, 2 0.8 5.5 v channel 3 0.8 13.5 v v fb1,2,3 regulated feedback voltage i th1,2,3 voltage = 1.2v, C55c to 150c (note 4) i th1,2,3 voltage = 1.2v, C40c to 125c (note 4) i th1,2,3 voltage = 1.2v, 0c to 85c (note 4) l l 0.790 0.792 0.794 0.800 0.800 0.800 0.810 0.808 0.806 v v v feedback current (note 4) C10 C50 na reference voltage line regulation v in = 6v to 24v (note 4) 0.002 0.02 %/v output voltage load regulation (note 4) measured in servo loop; di th voltage = 1.2v to 0.7v measured in servo loop; di th voltage = 1.2v to 1.6v l l 0.01 C0.01 0.1 C0.1 % % transconductance amplifier g m i th1,2,3 = 1.2v, sink/ source 5a (note 4) 2.2 mmho i q input dc supply current normal mode shutdown (note 5) v in = 15v v run1,2,3 = 0v 4.1 42 70 ma a uvlo undervoltage lockout on intv cc v intvcc ramping down 3.35 v uvlo hysteresis 0.5 v feedback overvoltage lockout measured at v fb1,2,3 (h-grade, mp-grade) measured at v fb1,2,3 l l 0.84 0.84 0.86 0.86 0.89 0.88 v v i sense sense pin current v sense = 3.3v 1 2 a soft-start charge current v tk/ss1,2,3 = 0v 0.9 1.3 1.7 a v run1,2,3 run pin on threshold v run1 , v run2 , v run3 rising l 1.1 1.2 1.35 v run pin hysteresis 80 mv maximum current sense threshold i th1,2,3 = 1.85v, v sense1,2,3 = 3.3v, i lim = 0v i th1,2,3 = 1.85v, v sense1,2,3 = 3.3v, i lim = 0v (h-, mp- grade) l l 22 21 30 30 38 39 mv mv i th1,2,3 = 1.85v, v sense1,2,3 = 3.3v, i lim = float i th1,2,3 = 1.85v , v sense1,2,3 = 3.3v , i lim = float ( h -, mp- grade) l l 42 41 50 50 58 59 mv mv i th1,2,3 = 1.85v, v sense1,2,3 = 3.3v, i lim = intv cc i th1,2,3 = 1.85v, v sense1,2,3 = 3.3v, i lim = intv cc (h-, mp-grade) l l 65 64 75 75 85 86 mv mv maximum duty factor in dropout 97 98 % tg driver pull-up on-resistance tg high 2.6 tg driver pull-down on-resistance tg low 1.5 bg driver pull-up on-resistance bg high 2.4 bg driver pull-down on-resistance bg low 1.1 tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns top gate off to bottom gate on delay synchronous switch-on delay time (note 6) c load = 3300pf each driver 30 ns ltc 3853 3853fc
4 for more information www.linear.com/ltc3853 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the junction temperature, t j , is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3853uj: t j = t a + (p d ? 33c/w) note 3: the ltc3853 is tested under pulsed load conditions such that t j t a . the ltc 3853e is guaranteed to meet performance specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc 3853i is guaranteed over the C40c to 125c operating junction temperature range. the ltc 3853h is guaranteed over the C40c to 150c operating junction temperature range and the ltc 3853mp is tested and the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 3), v in = 15v, v run1,2,3 = 5v, unless otherwise noted. guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 4: the ltc3853 is tested in a feedback loop that servos v ith1,2,3 to a specified voltage and measures the resultant v fb1,2,3 . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see the applications information section. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on- time considerations in the applications information section). symbol parameter conditions min typ max units bottom gate off to top gate on delay top switch-on delay time (note 6) c load = 3300pf each driver 30 ns t on(min) minimum on- time (note 7) 90 ns intv cc linear regulator v intvcc internal v cc voltage 7v < v in < 24v 4.8 5 5.2 v intv cc load regulation i cc = 0ma to 50ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v extv cc voltage drop i cc = 20ma, v extvcc = 5v 30 75 mv extv cc hysteresis 200 mv oscillator and phase-locked loop nominal frequency v freq = 1.2v 450 500 550 khz lowest frequency v freq = 0v 210 250 290 khz highest frequency v freq 2.4v 670 750 830 khz channel 2-channel 1 phase channel 3-channel 2 phase channel 1-channel 3 phase 120 120 120 deg deg deg channel 2-channel 1 phase channel 3-channel 2 phase channel 1-channel 3 phase v fb2 tied to v in through 200k 180 60 120 deg deg deg mode/pllin input resistance 250 k i freq phase detector output current sinking capability sourcing capability f mode < f osc f mode > f osc C13 13 a a pgood outputs pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 2 a pgood trip level v fb with respect to set regulated voltage v fb ramping negative v fb ramping positive C5 5 C 7.5 7.5 C10 10 % % ltc 3853 3853fc
5 for more information www.linear.com/ltc3853 typical performance characteristics efficiency vs output current and mode efficiency and power loss vs input voltage efficiency vs output current and mode load step (burst mode operation) load step (forced continuous mode) input voltage (v) 0 efficiency (%) power loss (mw) 75 80 85 15 25 3853 g03 70 65 60 5 10 20 90 95 100 1.0 0.8 1.2 1.4 0.4 0.6 0.2 0 1.6 1.8 2.0 30 v out = 3.3v i out = 2a figure 15 modified with dcr sensing efficiency power loss 40s/div v out 100mv/div ac coupled i l 2a/div i load 2a/div 3853 g04 v in = 12v v out = 3.3v i load = 0a to 3a figure 15 circuit 40s/div v out 100mv/div ac coupled i l 2a/div i load 2a/div 3853 g05 v in = 12v v out = 3.3v i load = 0a to 3a figure 15 circuit inductor current at light load load step (pulse skip mode) 40s/div v out 100mv/div ac coupled i l 2a/div i load 2a/div 3853 g06 v in = 12v v out = 3.3v i load = 0a to 3a figure 15 circuit 1s/div burst mode operation 2a/div forced continuous mode 2a/div pulse skipping mode 2a/div 3853 g07 v in = 12v v out = 1.8v i load = 100ma figure 15 circuit load current (a) 0.01 0.1 1 10 40 efficiency (%) 50 60 70 80 30 20 10 0 90 100 3853 g01 burst dcm ccm v in = 12v v out = 1.8v figure 15 modified with dcr sensing load current (a) 0.01 0.1 1 10 40 efficiency (%) 50 60 70 80 30 20 10 0 90 100 3853 g02 burst dcm ccm v in = 12v v out = 3.3v figure 15 modified with dcr sensing ltc 3853 3853fc
6 for more information www.linear.com/ltc3853 typical performance characteristics coincident tracking prebiased output at 2v maximum current sense voltage vs feedback voltage (current foldback) quiescent current vs input voltage without extv cc internal v cc line regulation current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage maximum current sense threshold vs duty cycle tracking up and down with external ramp 50ms/div v out 1v/div v tk/ss 500mv/div v fb 500mv/div 3853 g08 10ms/div v in = 12v v out1 = 3.3v v out2 = 2.5v v out3 = 1.8v run1 2v/div v out1,2,3 1v/div 3853 g09 5ms/div v in = 12v v out1 = 3.3v v out2 = 2.5v v out3 = 1.8v tk/ss1 tk/ss2 tk/ss3 2v/div v out1,2,3 1v/div 3853 g10 input voltage (v) 5 supply current (ma) 5.0 5.5 25 3853 g11 4.5 4.0 10 15 20 6.0 input voltage (v) 0 4.75 5.00 5.25 20 3853 g12 4.50 4.25 5 10 15 25 4.00 3.75 3.50 internal v cc (v) v ith (v) 0 ?40 v sense (mv) ?20 0 20 40 60 80 0.5 1 1.5 2 3853 g13 i lim = intv cc i lim = gnd i lim = float v sense common mode voltage (v) 0 current sense threshold (mv) 30 40 50 3 5 20 10 0 1 2 4 60 70 80 3853 g14 i lim = intv cc i lim = gnd i lim = float 60 80 100 40 20 50 70 90 30 10 0 duty cycle (%) 0 current sense threshold (mv) 60 100 20 40 80 3853 g15 i lim = intv cc i lim = gnd i lim = float feedback voltage (v) 0 maximum current sense voltage (mv) 40 50 60 0.8 3853 g16 30 20 0 0.2 0.4 0.6 0.1 0.9 0.3 0.5 0.7 10 80 70 i lim = intv cc i lim = float i lim = gnd ltc 3853 3853fc
7 for more information www.linear.com/ltc3853 typical performance characteristics tk/ss pull-up current vs temperature shutdown (run) threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature undervoltage lockout threshold ( intv cc ) vs temperature oscillator frequency vs input voltage temperature (c) tk/ss current (a) 3853 g17 ?60 ?40 ?20 20 40 80 100 140 1.30 1.35 1.40 1.45 1.50 1.60 0 60 120 160 1.55 temperature (c) 0.9 1.0 run pin voltage (v) 1.1 1.2 1.3 1.4 on 3853 g18 off ?60 ?40 ?20 20 40 80 100 140 0 60 120 160 temperature (c) 806 804 802 800 798 796 794 3853 g19 regulated feedback voltage (mv) ?60 ?40 ?20 20 40 80 100 140 0 60 120 160 ?60 ?40 ?20 20 40 80 100 140 0 60 120 160 temperature (c) 600 700 900 3853 g20 500 400 300 200 800 frequency (khz) v freq = intv cc v freq = 1.2v v freq = 0v temperature (c) ?50 intv cc voltage (v) 3.75 4.00 4.25 25 75 150 3853 g21 3.50 3.25 3.00 ?25 0 50 100 125 rising falling input voltage (v) 5 frequency (khz) 400 450 25 3853 g22 350 300 10 15 20 500 shutdown current vs input voltage shutdown current vs temperature quiescent current vs temperature without extv cc input voltage (v) 5 input current (a) 40 50 25 3853 g23 30 20 10 15 20 60 temperature (c) shutdown current (a) 3853 g24 ?60 ?40 ?20 20 40 80 100 140 20 25 30 35 40 60 0 60 120 160 50 45 55 temperature (c) quiescent current (ma) 3853 g25 ?60 ?40 ?20 20 40 80 100 140 3.0 3.5 4.0 4.5 5.0 6.0 0 60 120 160 5.5 ltc 3853 3853fc
8 for more information www.linear.com/ltc3853 pin functions sense1 + , sense2 + , sense3 + ( pins 3, 5, 7): current sense comparator inputs. the (+) inputs to the current compara - tors are normally connected to dcr sensing networks or current sensing resistors. sense3 + common modes up to 13.5v, allowing higher v out voltages on channel 3. sense1 C , sense2 C , sense3 C (pins 4, 6, 8): current sense comparator inputs. the (C) inputs to the current comparators are connected to the outputs. sense3 C com - mon modes up to 13.5v, allowing higher v out voltages on channel 3. v fb 1 , v fb 2 , v fb 3 ( pins 9, 12, 14): error amplifier feedback inputs. these pins receive the remotely sensed feedback voltages for each channel from external resistive dividers across the outputs. connecting v fb2 to v in through a 200k resistor enables dual output (2 + 1) mode. i th1 , i th2 , i th3 (pins 10, 13, 15): current control thresh - olds and error amplifier compensation points. each as - sociated channels current comparator tripping threshold increases with its i th control voltage. in dual output (2 + 1) mode, i th1 and i th2 need to be shorted externally. sgnd (pin 11): signal ground. all small-signal compo - nents and compensation components should connect to this ground, which in turn connects to pgnd at one point. pgood3 (pin 16): power good indicator output for phase 3. open-drain logic out that is pulled to ground when any channel output exceeds the 7.5% regulation window, after the internal 17s power bad mask timer expires. pgood12 (pin 17): power good indicator output for phases 1 and 2. open-drain logic out that is pulled to ground when any channel output exceeds the 7.5% regulation window, after the internal 17s power bad mask timer expires. intv cc (pin 22): internal 5v regulator output. the control circuits are powered from this voltage. also provides channel 3 driver power. decouple this pin to pgnd with a minimum of 4.7f low esr tantalum or ceramic capacitor. extv cc ( pin 23): external power input to an internal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7v. do not exceed 6v on this pin and ensure v in > v extvcc at all times. v in (pin 24): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). drv cc12 (pin 29): driver voltage input for channels 1 and 2. do not exceed 6v on this pin. this pin must be tied to intv cc externally. bg1, bg2, bg3 (pins 30, 28, 21): bottom gate driver outputs. these pins drive the gates of the bottom n- channel mosfets between pgnd and intv cc / drv cc12 . sw1, sw2, sw3 (pins 31, 27, 20): switch node con - nections to inductors. voltage swing at these pins is from a schottky diode ( external) voltage drop below ground to v in . tg1, tg2, tg3 (pins 32, 26, 19): top gate driver outputs. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch nodes voltages. boost1, boost2, boost3 (pins 33, 25, 18): boosted floating driver supplies. the (+) terminal of the boot - strap capacitors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . ltc 3853 3853fc
9 for more information www.linear.com/ltc3853 run1, run2, run3 (pins 36, 35, 34): run control in - puts. a voltage above 1.2v on any run pin turns on the ic. however, forcing any of these pins below 1.2v causes the ic to shut down the circuitry required for that particular channel. there are 0.5a pull-up currents for these pins. once the run pin rises above 1.2v, an additional 4.5a pull-up current is added to the pin. mode/pllin (pin 37): force continuous mode, burst mode, or pulse skip mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force all channels into the continuous mode of operation. connect to intv cc to enable pulse skip mode of operation. leaving the pin floating will en - able burst mode operation. a clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator. freq/ pllfltr (pin 38): the phase-locked loops low - pass filter is tied to this pin. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. i lim (pin 39): current comparator sense voltage range inputs. this pin is to be programmed to sgnd, float or intv cc to set the maximum current sense threshold to three different levels. tk/ss1, tk/ss2, tk/ss 3 (pins 40, 1, 2): output voltage tracking and soft- start inputs. when one particular channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when the channel is configured to be the slave, the v fb voltage of the master channel is reproduced by a resistor divider and applied to this pin. internal soft-start currents of 1.3a are charging the soft-start capacitors. in dual output (2 + 1) mode, tk/ss1 and tk/ss2 need to be shorted externally. pgnd (exposed pad pin 41): power ground. connect this pin close to the sources of the bottom n - channel mosfets , the (C) terminal of c vcc and the (C) terminal of c in . pin functions ltc 3853 3853fc
10 for more information www.linear.com/ltc3853 functional diagram 4.7v ? + ? + ? + ? + v in 0.5a slope compensation uvlo slope recovery active clamp osc s rq 3k run switch logic and anti- shoot through bg on fcnt 0.8v ov 1 51k 1.2v 0.64v i th r c intv cc intv cc i lim i thb i cmp c c1 ea ss sgnd r1 0.86v r2 run pgnd pgood intv cc extv cc i rev sw tg c b v in c in v in sleep boost bursten ? + ? + uv ov c vcc v out c out m2 m1 l1 d b mode/pllin sense + sense ? ? + 0.8v ref tk/ss run 0.55v ? + v fb freq/pllfltr pll-sync mode/sync detect + + 5v reg 1.3a c ss + ? + ? + f f 0.74v 3853 fd ltc 3853 3853fc
11 for more information www.linear.com/ltc3853 operation main control loop the ltc3853 is a constant- frequency, current mode step-down controller with three channels operating 120 degrees out-of-phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of each error amplifier, ea. the v fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator i rev , or the beginning of the next cycle. intv cc / extv cc / drv cc12 power power for the top and bottom mosfet drivers of phase 3 and most other internal circuitry is derived from the intv cc pin. drv cc12 provides driver power for phase 1 and phase 2. this pin must be externally tied to intv cc . if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc . using the extv cc pin allows the intv cc power to be de - rived from a high efficiency external source such as one of the ltc3853 switching regulator outputs. each top mosfet driver is biased from the floating boot - strap capacitor, c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detec - tor detects this and forces the top mosfet off for about one-twelfth of the clock period every fifth cycle to allow c b to recharge. however, it is recommended that there is always a load be present during the dropout transition to ensure c b is recharged. shutdown and start-up (run1, run2, run3 and tk/ ss1, tk/ss2, tk/ss3 pins) the three channels of the ltc3853 can be independently shut down using the run1, run2 and run3 pins. pulling any of these pins below 1.2v shuts down the main control loop for that controller. pulling all pins low disables all three controllers and most internal circuits , including the intv cc regulator. releasing any run pin allows an internal 0.5a current to pull up the pin and enable that controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of each controllers output voltage v out is controlled by the voltage on the tk/ss1, tk/ss2 and tk/ss3 pins. when the voltage on the tk/ss pin is less than the 0.8v internal reference, the ltc3853 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.8v reference. this allows the tk/ss pin to be used to program a soft-start by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.3a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.8v (and beyond), the output voltage v out rises smoothly from zero to its final value. alternatively the tk/ ss pin can be used to cause the start-up of v out to track that of another supply. typically , this requires connect - ing to the tk/ss pin an external resistor divider from the other supply to ground (see the applications information section). when the corresponding run pin is pulled low to disable a controller, or when intv cc drops below its undervoltage lockout threshold of 3.35v, the tk/ss pin is pulled low by an internal mosfet. when in undervolt - age lockout, all controllers are disabled and the external mosfets are held off. light load current operation (burst mode operation, pulse skipping or continuous conduction) the ltc3853 can be enabled to enter high efficiency burst mode operation, constant- frequency pulse skipping mode, or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to a dc voltage below 0.8v (e.g., sgnd). to select pulse skipping ltc 3853 3853fc
12 for more information www.linear.com/ltc3853 mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. when the controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator ( i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from revers - ing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur - rent is determined by the voltage on the i th pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the ltc3853 operates in pwm pulse skipping mode at light loads. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq/ pllfltr and mode/pllin pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/ or capacitance to main - tain low output ripple voltage. the switching frequency of the ltc3853s controllers can be selected using the freq/ pllfltr pin. if the mode/pllin pin is not being driven by an external clock source , the freq/ pllfltr pin can be used to program the controllers operating frequency from 250khz to 750khz. a phase-locked loop (pll) is available on the ltc3853 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller is operating in forced continuous mode when it is synchronized. a series r-c should be connected between the freq/ pllfltr pin and sgnd to serve as the plls loop filter. power good (pgood12 and pgood3 pins) the pgood12 pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood12 pin low when either v fb1 or v fb2 pin voltage is not within 7.5% of the 0.8v reference voltage. the pgood12 pin is also pulled low when either run1 or run2 pin is below 1.2v or when the ltc3853 is in the soft-start or tracking phase. when the v fb pin voltage is within the 7.5% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood12 pin will flag power good immediately when both v fb1 and v fb2 pins are within the 7.5% window. however, there is an internal 17s power bad mask when either v fb is out of the 7.5% window. pgood3 monitors v fb3 and is also pulled low when run3 is below 1.2v. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (> 7.5%) as well as other more serious con - ditions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. operation ltc 3853 3853fc
13 for more information www.linear.com/ltc3853 triple vs dual (2 + 1) operation the ltc3853 can be used to regulate three different out - puts. it can also be used as a dual output controller with a high current 2-phase output and a single phase output. tying v fb2 to v in through a 200k resistor switches the controller from triple to dual (2 + 1) operation. do not ex - ceed the absolute maximum current rating for the v fb2 pin. in dual (2 + 1) mode, phase 1 and phase 2 are 180 degrees apart (instead of 120 degrees) with phase 3 remaining at operation 240 degrees from phase 1. the i th1 and i th2 pins must be shorted together externally and so must the tk/ss1 and tk/ss2 pins for proper operating of the 2 phase portion of the controller. run2 should be grounded. run1 will now control both phases 1 and 2, while run3 continues to control the turn on of phase 3. phase 3 is also capable of regulating up to a 13.5v output in either mode, while phases 1 and 2 are limited to a 5.3v output. applications information the typical application on the first page is a basic ltc3853 application circuit . ltc3853 can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resis - tors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load require - ment, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maxi - mum current limit of the controller. when i lim is either grounded, floated or tied to intv cc , the typical value for the maximum current sense threshold will be 30mv, 50mv or 75mv, respectively. which setting should be used? for the best current limit accuracy, use the 75mv setting. the 30mv setting will allow for the use of very low dcr inductors or sense resistors, but at the expense of current limit accuracy. the 50mv setting is a good balance between the two. for single output dual phase applications ((2 + 1) mode), use the 50mv or 75mv setting for optimal current sharing. sense + and sense C pins the sense + and sense C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0v to 5.3v for phases 1 and 2, and 0v to 13.5v for phase 3. both sense pins are high impedance inputs with small base currents of less than 1a. when the sense pins ramp up from 0v to 1.4v, the small base currents flow out of the sense pins. when the sense pins ramp down from the maximum common mode voltage to 1.1v, the small base currents flow into the sense pins. the high impedance inputs to the cur - rent comparators allow accurate dcr sensing. however, care must be taken not to float these pins during normal operation. filter components mutual to the sense lines should be placed close to the ltc3853, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading figure 1. sense lines placement with inductor or sense resistor c out to sense filter, next to the controller inductor or r sense 3853 f01 ltc 3853 3853fc
14 for more information www.linear.com/ltc3853 applications information figure 2. tw o different methods of sensing current (2a) using a resistor to sense current (2b) using the inductor dcr to sense current v in v in intv cc boost tg sw bg pgnd filter components placed near sense pins sense + sense ? sgnd ltc3853 r s r f r f c f esl l1 3853 f02a r sense v in v in intv cc boost tg sw bg pgnd *place c1 near sense + , sense ? pins inductor dcr l sense + sense ? sgnd ltc3853 v out 3853 f02b r1 r2 c1* r1 || r2 c1 = l dcr r sense(eq) = dcr r2 r1 + r2 the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. low value resistors current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, di l . to calculate the sense resistor value, use the equation: r s e n s e = v s e n s e ( m a x ) i ( m a x ) + ? i l 2 because of possible pcb noise in the current sensing loop, the ac current sensing ripple of dv sense = di l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, a 15mv dv sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications. for previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mv for the ltc1628 / ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. for todays highest current density solutions, however, the value of the sense resistor can be less than 1m? and the peak sense voltage can be as low as 20mv. in addition, inductor ripple currents greater than 50% with operation up to 1mhz are becoming more com - mon. under these conditions the voltage drop across the sense resistor s parasitic inductance is no longer negligible. a typical sensing circuit using a discrete resistor is shown in figure 2a. in previous generations of controllers, a small rc filter placed near the ic was commonly used to reduce the effects of capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 10? resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns. this same rc filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. ltc 3853 3853fc
15 for more information www.linear.com/ltc3853 for example, figure 3 illustrates the voltage waveform across a 2m? sense resistor with a 2010 footprint for the 1.2v /15a converter operating at 100% load. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: es l = v e s l ( s t e p ) ? i l t o n ? t o f f t o n + t o f f if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor (l/r), the result - ing waveform looks resistive again, as shown in figure 4. for applications using low maximum sense voltages, check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of applications information data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use the equation above to determine the esl. however, do not over-filter. keep the rc time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on v rsense . the above generally applies to high density/high current applications where i (max) > 10a and low values of induc - tors are used. for applications where i (max) < 10a, set r f to 10 and c f to 1000pf. this will provide a good starting point. the filter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin connected to the sense resistor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3853 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing . if the external r1||r 2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r 2/(r 1 + r 2). r 2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r s e n s e ( e q u i v ) = v s e n s e ( m a x ) i ( m a x ) + ? i l 2 500ns/div v sense 20mv/div 3853 f03 v esl(step) 500ns/div v sense 20mv/div 3853 f04 figure 3. voltage waveform measured directly across the sense resistor figure 4. voltage waveform measured after the sense resistor filter. c f = 1000pf, r f = 100 ltc 3853 3853fc
16 for more information www.linear.com/ltc3853 to ensure that the application will deliver full load cur - rent over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (22mv, 42mv, or 65mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. where pro - vided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the tem - perature coefficient of resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r s e n s e ( e q u i v ) d c r ( m a x ) a t t l ( m a x ) c1 is usually selected to be in the range of 0.047f to 0.47f. this forces r1||r2 to around 2k, reducing error that might have been caused by the sense pins 1a current. the equivalent resistance r1||r2 is scaled to the room temperature inductance and maximum dcr: r 1 || r 2 = l ( d c r a t 20 c ) ? c 1 the sense resistor values are: r 1 = r 1 || r 2 r d ; r 2 = r 1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p l o s s r 1 = v i n ( m a x ) ? v o u t ( ) ? v o u t r 1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, re - duces conduction losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. to maintain a good signal-to-noise ratio for the current sense signal, use a minimum dv sense of 10mv to 15mv. for a dcr sensing application, the actual ripple voltage will be determined by: ? v s e n s e = v i n C v o u t r 1 ? c 1 ? v o u t v i n ? f o s c slope compensation and inductor peak current slope compensation provides stability in constant- frequency architectures by preventing subharmonic oscillations at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak cur - rent for duty cycles >40%. however, the ltc3853 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i r i p p l e = v o u t v i n v i n C v o u t f o s c ? l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v i n C v o u t f o s c ? i r i p p l e ? v o u t v i n applications information ltc 3853 3853fc
17 for more information www.linear.com/ltc3853 inductor core selection once the inductance value is determined, the type of in - ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection tw o external power mosfets must be selected for each controller in the ltc3853: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc / drv cc12 voltage. this voltage is typically 5v during start- up ( see extv cc pin connection). consequently, logic- level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets ( v gs(th) < 3v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: m a i n s wi t c h d ut y c y c l e = v o u t v i n s y nc hr onous s wi t c h d ut y c y c l e = v i n C v o u t v i n the mosfet power dissipations at maximum output current are given by: p m a i n = v o u t v i n i m a x ( ) 2 1 + ( ) r d s ( o n ) + v i n ( ) 2 i m a x 2 ? ? ? ? ? ? r d r ( ) c m i l l e r ( ) ? 1 v i n t v c c C v t h ( m i n ) + 1 v t h ( m i n ) ? ? ? ? ? ? ? ? ? f o s c p s y n c = v i n C v o u t v i n i m a x ( ) 2 1 + ( ) r d s ( o n ) where d is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n - channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets , while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short- circuit when the synchronous switch is on close to 100% of the period. the term (1 + d) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve , but d = 0.005/c can be used as an approximation for low voltage mosfets. applications information ltc 3853 3853fc
18 for more information www.linear.com/ltc3853 applications information the optional schottky diodes conduct during the dead time between the conduction of the two power mosfets . these prevent the body diodes of the bottom mosfets from turn - ing on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. soft-start and tracking the ltc3853 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply . when one particular channel is configured to soft-start by itself, a capacitor should be connected to its tk/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.2v. its tk/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.2v, the channel pow - ers up. a soft-start current of 1.3a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0v to 0.8v on the tk/ss pin. the total soft-start time can be calculated as: t s o f t s t a r t = 0.8 ? c s s 1.3 a regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse skipping mode up to tk/ss = 0.64v. between tk/ss = 0.64v and 0.74v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.74v. the output ripple is minimized during the 100mv forced continuous mode window ensuring a clean pgood signal. when the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft- start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the ltc3853 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.74v regardless of the setting of the mode/pllin pin. however, the ltc3853 should always be set in force continuous mode tracking down when there is no load. after tk/ss drops below 0.1v, its channel will operate in discontinuous mode. output voltage tracking the ltc3853 allows the user to program how its out - put ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to ei - ther coincidentally or ratiometrically track another supplys output, as shown in figure 5. in the following discussions, v out1 refers to the ltc3853s output 1 as a master channel and v out 2 refers to the ltc3853 s output 2 as a slave channel. in practice though, any phase can be used as the master. to implement the coincident track - ing in figure 5a, connect an additional resistive divider to v out1 and connect its midpoint to the tk/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 6a. in this tracking mode, v out1 must be set higher than v out 2 . to implement the ratiometric tracking , the ratio of the slaves divider should be exactly the same as the master channels feedback divider. by selecting different resistors, the ltc3853 can achieve different modes of tracking including the two in figure 5. so which mode should be programmed? while either mode in figure 6 satisfies most practical applications, there are some trade-offs. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. this can be better understood with the help of figure 7. at the input stage of the slave channels error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same amplitude. in the ltc 3853 3853fc
19 for more information www.linear.com/ltc3853 figure 7. equivalent input circuit of error amplifier figure 5. tw o different modes of output voltage tracking figure 6. setup for coincident and ratiometric tracking applications information time (5a) coincident tracking v out1 v out2 output voltage 3853 f05a v out1 v out2 time 3853 f05b (5b) ratiometric tracking output voltage r3 r1 r4 r2 r3 v out2 r4 (6a) coincident tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3853 f06 (6b) ratiometric tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 ? + i i d1 tk/ss2 0.8v v fb2 d2 d3 3853 f07 ea2 coincident mode, the tk/ss voltage is substantially higher than 0.8v at steady state and effectively turns off d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb2 and the internal precision 0.8v reference. in the ratiometric mode, however, tk/ss equals 0.8v at steady state. d1 will divert part of the bias current to make v fb2 slightly lower than 0.8v. although this error is minimized by the exponential i-v characteristic of the diode, it does impose a finite amount of output voltage deviation. furthermore, when the master channels output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. intv cc regulators and extv cc the ltc3853 features an npn linear regulator that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the ltc3853s internal circuitry . the linear regulator regulates the voltage at the intv cc pin to 5v when v in is greater than 6.5v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7v. each of these can supply a peak current of 150ma and must be bypassed to ground with a minimum of 1f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing ltc 3853 3853fc
20 for more information www.linear.com/ltc3853 is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc3853 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5 v linear regulator or extv cc . when the voltage on the extv cc pin is less than 4.7v, the linear regulator is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the ltc3853 intv cc current is limited to less than 50ma from a 24v supply in the uj package and not using the extv cc supply: t j = 85c + (50ma)(24v)(33c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode ( mode/ pllin = sgnd) at maximum v in . when the voltage applied to ext - v cc rises above 4.7v, the intv cc linear regulator is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5v. using the extv cc allows the mosfet driver and control power to be derived from one of the ltc3853 s switching regulator outputs during normal operation and from the intv cc when the output is out of regulation (e.g., start-up, short- circuit). if more current is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc < v in . significant efficiency and thermal gains can be realized by powering intv cc from the output, since the v in cur - rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 85c + (50ma)(5v)(33c/w) = 94c however, for 3.3v and other low voltage outputs, additional circuitry is required to derive intv cc power from the output . the following list summarizes the four possible connec - tions for extv cc : 1. extv cc left open ( or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if a 5 v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost net- work. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. for applications where the main input power is 5v, tie the v in and intv cc pins together and tie the combined pins to the 5v input with a 1 or 2.2 resistor as shown in figure 8 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic-level devices. applications information intv cc ltc3853 r vin 1 c in 3853 f08 5v c intvcc 4.7f + v in figure 8. setup for a 5v input ltc 3853 3853fc
21 for more information www.linear.com/ltc3853 topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins supply the gate drive voltages for the topside mos - fets . capacitor c b in the functional diagram is charged though external diode, d b , from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet( s ). the reverse breakdown of the external schottky diode must be greater than v in( max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. undervoltage lockout the ltc3853 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.35v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 500mv of preci - sion hysteresis. another way to detect an undervoltage condition is to monitor the v in supply. because the run pins have a precision turn- on reference of 1.2v , one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5a of current flows out of the run pin once the run pin voltage passes 1.2v . one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. for accurate v in undervoltage detection using the run pin, v in needs to be higher than 4 v . c in and c out selection the selection of c in is simplified by the 3-phase architec - ture and its impact on the worst-case rms current drawn through the input network ( battery / fuse/ capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output current drawn from the other controllers will actually decrease the input rms ripple current from its maximum value. the out-of- phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode , the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c i n r e qui r e d i r m s i m a x v i n v o u t ( ) v i n C v o u t ( ) ? ? ? ? 1 / 2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3853, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the ltc3853 3-phase operation can be cal - culated by using the equation above for the higher power controller and then calculating the loss that would have resulted if all controller channels switched on at the same time. the total rms power lost is lower when more than one controller is operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the applications information ltc 3853 3853fc
22 for more information www.linear.com/ltc3853 dual or triple controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 3-phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/ battery is included in the efficiency testing. the sources of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may pro - duce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3853, is also suggested. a 2.2 to 10 resistor placed between c in and the v in pin provides further isolation between the channels. the selection of c out is driven by the effective series resistance (esr). typically , once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (dv out ) is approximated by: ? v o u t i r i p p l e es r + 1 8 f c o u t ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc - tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the ltc3853 output voltages are each set by an external feedback resistive divider carefully placed across the out - put, as shown in figure 9. the regulated output voltage is determined by: v o u t = 0.8 v ? 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feed- forward ca - pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources , such as the inductor or the sw line. figure 9. setting output voltage applications information 1/3 ltc3853 v fb v out r b c ff r a 3853 f09 fault conditions: current limit and current foldback the ltc3853 includes current foldback to help limit load current when the output is shorted to ground. if the out - put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one- third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short- circuit conditions with very low duty cycles, the ltc3853 will begin cycle skipping in order to limit the short- circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on- time t on(min) of the ltc3853 ( 90ns), the input voltage and inductor value: ? i l ( s c ) = t o n ( m i n ) ? v i n l the resulting short- circuit current is: i s c = 1 / 3 v s e n s e ( m a x ) r s e n s e C 1 2 ? i l ( s c ) ltc 3853 3853fc
23 for more information www.linear.com/ltc3853 figure 10. relationship between oscillator frequency and voltage at the freq/ pllfltr pin phase-locked loop and frequency synchronization the ltc3853 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the external filter network connected to the freq/ pllfltr pin. the relationship between the voltage on the freq/ pllfltr pin and operating frequency is shown in figure 10 and specified in the electrical characteristics table. note that the ltc3853 can only be synchronized to an external clock whose frequency is within range of the ltc3853s internal v co . this is guaranteed to be between 250khz and 750khz. a simplified block diagram is shown in figure 11. if the external clock frequency is greater than the internal oscillators frequency, f osc , or if the external clocks phase lags the internal oscillator, then current is sourced from the phase detector output, pulling up the freq/ pllfltr pin. when the external clock frequency is less than f osc , or if the external clocks phase leads the internal oscilla - tor, current is sunk, pulling down the freq/ pllfltr pin. the voltage on the freq/ pllfltr pin is adjusted until the phase and frequency of the internal and external oscilla - tors are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor, c lp , holds the voltage. the loop filter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10 k and c lp is 2200pf to 0.01f. typically , the external clock ( on mode/ pllin pin) input high threshold is 1.6v, while the input low threshold is 1v. minimum on- time considerations minimum on-time t on(min) is the smallest time duration that the ltc3853 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t o n ( m i n ) < v o u t v i n ( f ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. figure 11. phase-locked loop block diagram applications information freq/pllfltr pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3853 f10 2.5 300 400 500 800 700 200 600 digital phase/ frequency detector vco 2.4v r lp c lp 3853 f11 freq/ pllfltr external oscillator mode/ pllin ltc 3853 3853fc
24 for more information www.linear.com/ltc3853 the minimum on-time for the ltc3853 is approximately 90ns, with reasonably good pcb layout, minimum 30% inductor current ripple and at least 10mv to 15mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. however, as the peak sense voltage decreases the minimum on-time gradually increases to 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3853 circuits : 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typi - cally results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets . each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur - rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through extv cc from an output- derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20v to 5v applica - tion, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor, current sense resistor. in continuous mode, the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 10m, r l = 10m, r sense = 5m, then the total resistance is 25m. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maxi - mum of 20m to 50m of esr. the ltc3853 3-phase architecture reduces this input capacitance requirement up applications information ltc 3853 3853fc
25 for more information www.linear.com/ltc3853 to 66% over competing solutions. other losses including schottky conduction losses during dead time and induc - tor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to di load (esr), where esr is the effective series resistance of c out . di load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control-loop behavior but also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without break - ing the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be in - creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. applications information ltc 3853 3853fc
26 for more information www.linear.com/ltc3853 applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. figure 12 illustrates the current waveforms pres - ent in the various branches of the 3-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets located within 1 cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the three channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter - minals. the v fb and i th traces should be as short as possible. the path formed by the top n-channel mos - fet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3853 v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense + and sense C leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed im - mediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw), top gate nodes (tg), and boost nodes (boost) away from sensitive small- signal nodes, especially from another channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3853 and occupy minimum pc trace area . if dcr sensing is used, place the top resistor (figure 2b, r1) close to the switching node. 7. use a modified star ground technique: a low imped - ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. ltc 3853 3853fc
27 for more information www.linear.com/ltc3853 figure 12. branch current waveforms applications information r l1 l1 sw1 v out1 c out1 + v in r sense1 r sense2 r sense3 c in r in + r l3 bold lines indicate high switching currents. keep lines to a minimum length. l3 sw3 3853 f12 v out3 c out3 + d2 r l2 l2 sw2 v out2 c out2 + d1 d3 ltc 3853 3853fc
28 for more information www.linear.com/ltc3853 pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit . monitor the output switching node ( sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% of the maximum designed cur - rent level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well- designed, low noise pcb implemen - tation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensa - tion of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should all controllers be turned on at the same time. a particularly difficult region of operation is when one con - troller channel is nearing its current comparator trip point when another channel is turning on its top mosfet. this occurs around 33% and 66% duty cycle on a channel in triple mode, due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. design example as a design example for a three channel medium cur - rent regulator, assume v in = 12v ( nominal), v in = 20v(maximum), v out1 = 5v, v out2 = 3.3v, v out3 = 1.2v, i max1,2,3 = 5a, and f = 500khz (see figure 13). the regulated output voltages are determined by: v o u t = 0.8 v ? 1 + r b r a ? ? ? ? ? ? using 20k 1% resistors from both v fb nodes to ground, the top feedback resistors are (to the nearest 1% standard value) 105k, 63.4k and 10k. the minimum on- time occurs on channel 3 at the maximum v in , and should not be less than 90ns: t o n ( m i n ) = v o u t v i n ( m a x ) f = 1.2 v 20 v ( 500 k h z ) = 120 ns the frequency is set by biasing the freq/ pllfltr pin to 1.2v (see figure 10), using a divider from intv cc . this voltage will decrease as v in approaches 5v, lowering the switching frequency. if a separate 5v supply is connected to extv cc , intv cc will remain at 5v even if v in decreases. the inductance values are based on a 35% ripple current assumption (1.75a for each channel) at nominal input voltage: l = v o u t f ? ? i l ( n o m ) 1 ? v o u t v i n ( n o m ) ? ? ? ? ? ? channel 1 will require 3.3h, channel 2 will require 2.8h and channel 3 will require 1.25h. the next highest standard values are 3.3h, 3.3h and 1.5h. at the maximum input voltage (20v), the ripple will be: ? i l ( m a x ) = v o u t f ? l 1 ? v o u t v i n ( m a x ) ? ? ? ? ? ? applications information ltc 3853 3853fc
29 for more information www.linear.com/ltc3853 channel 1 will have ~2.3a (46%) ripple, and both channel 2 and channel 3 will have ~1.75a (35%) ripple. the peak inductor current will be the maximum dc value plus one- half the ripple current, or 6.15a for channel 1 and 5.88a for channels 2 and 3. with i lim high, the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (65mv). r s e n s e ( e q u i v ) = v s e n s e ( m i n ) i l o a d ( m a x ) + ? i l ( n o m ) 2 = 65 m v 1.2 ? 5 a + ? i l ( m a x ) 2 ? ? ? ? ? ? ? 9 m the 1.2 factor adds margin for component variation and overcurrent headroom during full load transients. the equivalent r sense is the same for channels 1, 2 and 3. the vishay ihlp2525czer3r3m01 (30m dcr max at 20c) and ihlp2525czer1r5m01 (15m dcr max at 20c ,) are chosen. at 100c , the estimated maximum dcr values are 39.6mv and 19.8mv. the divider ratios are: r d = r s e n s e ( e q u i v ) d c r m a x a t t l ( m a x ) = 9 m 39.6 m = 0.23 ; a nd 9 m 19.8 m ? 0.45 for each channel, 0.1f is selected for c1. r 1 || r 2 = l ( d c r m a x a t 20 c ) ? c 1 = 3.3 h 30 m ? 0.1 f = 1100 a nd 1.5 h 15 m ? 0.1 f = 1000 applications information figure 13. high efficiency triple 5v/3.3v/1.2v step-down converter tg1 tg2 boost1,2,3 sw1 sw2 bg1 bg2 sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1,2,3 v in intv cc ltc3853 drv cc12 mode/pllin 20k 1% freq/pllfltr ilim pgnd pgood12 sgnd extv cc tk/ss1,2,3 v fb3 sense3 ? sense3 + sw3 tg3 bg3 run1,2,3 pgood3 4.75k 1430 20k 1% 3.16k 1nf 63.4k 1% 4.7f 10k intv cc v out1 5v 5a v out2 3.3v 5a 20k 1% 3853 f13 2.43k 4.75k v out3 1.2v 5a v in 7v to 20v c ith1,2,3 r ith1,2,3 0.1f 330f 10v m1, m2, m3: si4816bdy channel 1: r ith1 = 15k, c ith1 = 1.5nf, c p1 = 220pf channel 2: r ith2 = 18k, c ith2 = 1.5nf, c p2 = 220pf channel 3: r ith3 = 10k, c ith3 = 1.5nf, c p3 = 330pf for channel 3, 0.068f was substituted for 0.1f and 2.43k was substituted for 2.21k to meet minimum 15mv ripple at sense input requirement c p1,2,3 22f 50v c ss1,2,3 0.1f 0.1f 10pf 1430 3.3h 3.3h 1.5h c b1,2,3 0.1f sw1,2,3 d b1,2,3 m2 m1 m3 0.068f 1.82k + 330f 6v + 330f 6v + 10k 1% 105k 1% 10pf ltc 3853 3853fc
30 for more information www.linear.com/ltc3853 for channel 1, the dcr sense filter/divider values are: r 1 = r 1 || r 2 r d = 1100 0.23 ? 4.75 k ; r 2 = r 1 ? r d 1 ? r d = 4.75 k ? 0.23 1 ? 0.23 ? 1430 the power loss in r1 at the maximum input voltage is: p l o s s r 1 = ( v i n ( m a x ) ? v o u t ) ? v o u t r 1 = ( 20 v ? 5 v ) ? 5 v 4.75 k = 15.8 m w the respective values for channel 2 are r 1 = 4.75k, r 2 = 1430; and p loss r 1 = 11.6mw. and for channel 3 are r1 = 2.21k, r2 = 1.82k; and p loss r1 = 10.2mw. burst mode operation is chosen for high light load efficiency (figure 14) by floating the mode/pllin pin. power loss due to the dcr sensing network is slightly higher at light loads than would have been the case with a suitable sense resistor (9m). at heavier loads, dcr sensing provides higher efficiency. the power dissipation on the topside mosfet can be easily estimated. choosing a siliconix si4816bdy dual mosfet results in: r ds(on) = 0.023/0.016, c miller @ 100pf. at maximum input voltage with t(estimated) = 50c: p m a i n = 5 v 20 v 5 ( ) 2 1 + ( 0.005 ) ( 50 c C 25 c ) [ ] ? 0.023 ( ) + 20 v ( ) 2 5 a 2 ? ? ? ? ? ? 2 ( ) 100 pf ( ) ? 1 5 C 2.3 + 1 2.3 ? ? ? ? ? ? 500 k h z ( ) = 243 m w a short- circuit to ground will result in a folded back cur - rent of: i s c = 1 / 3 ( ) 75 m v 0.009 C 1 2 90 ns ( 20 v ) 3.3 h ? ? ? ? ? ? = 2.5 a with a typical value of r ds(on) and d = (0.005/c)(25) = 0.125. the resulting power dissipated in the bottom mosfet is: p s y n c = 20 v C 5 v 20 v 2.5 a ( ) 2 1.125 ( ) 0.016 ( ) = 84 m w which is less than under full-load conditions. c in is chosen for an rms current rating of at least 2a at temperature assuming only one channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (di l ) = 0.02(1.5a) = 30mv p-p figure 14. design example efficiency vs load applications information load current (a) 0.01 70 efficiency (%) power loss (mw) 80 90 0.1 1 10 60 50 40 100 0.1 1 0.01 10 3853 f14 efficiency power loss dcr 9m dcr ltc 3853 3853fc
31 for more information www.linear.com/ltc3853 figure 15. triple 2.5v/1.8v/3.3v 5a step-down converter with r sense , f sw = 500khz tg1 tg2 boost1,2,3 sw1 sw2 bg1 bg2 sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1,2,3 v in intv cc drv cc12 ltc3853 mode/pllin 20k 1% freq/pllfltr ilim pgnd pgood12 sgnd extv cc tk/ss1,2,3 v fb3 sense3 ? sense3 + sw3 tg3 bg3 run1,2,3 pgood3 10* 10* 20k 1% 3.16k 24.9k 1% 4.7f 10k intv cc v out1 2.5v 5a v out2 1.8v 5a 20k 1% 0.008 5% v out3 3.3v 5a v in 7v to 24v c ith1,2,3 r ith1,2,3 1000pf* 220f 4v m1, m2, m3: si4816bdy channel 1: r ith1 = 18k, c ith1 = 1500pf, c p1 = 220pf channel 2: r ith2 = 12k, c ith2 = 1500pf, c p2 = 220pf channel 3: r ith3 = 18k, c ith3 = 1500pf, c p3 = 220pf c p1,2,3 33f 35v c ss1,2,3 0.1f *these filter components need to be close to the ic 1000pf 1000pf* 1000pf* 10* 10* 1.5h 1.5h 2.2h 10pf c b1,2,3 0.1f sw1,2,3 d b1,2,3 m2 m1 m3 10* + 220f 4v + 220f 4v 3853 f15 + 63.4k 1% 10* 43.2k 1% 0.008 5% 10pf 0.008 5% applications information ltc 3853 3853fc
32 for more information www.linear.com/ltc3853 typical applications triple 3.3 v /2.5 v /12 v , 5 a step - down converter with r sense synchronized at 400 khz tg1 tg2 boost1,2,3 sw1 sw2 bg1 bg2 sense1 + mode/pllin sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1,2,3 v in intv cc drv cc12 ltc3853 20k 1% freq/pllfltr ilim pgnd pgood12 sgnd tk/ss1,2,3 v fb3 sense3 ? sense3 + sw3 tg3 bg3 run1,2,3 pgood3 10* 10* 20k 1% 10k 43.2k 1% 4.7f v out1 3.3v 5a v out2 2.5v 5a 10k 1% 0.008 5% v out3 12v 4a v in 13v to 24v c ith1,2,3 r ith1,2,3 1000pf* pllin 400khz 220f 4v m1, m2, m3: si4816bdy channel 1: r ith1 = 18k, c ith1 = 1500pf, c p1 = 220pf channel 2: r ith2 = 18k, c ith2 = 1500pf, c p2 = 220pf channel 3: r ith3 = 43k, c ith3 = 470pf, c p3 = 330pf c p1,2,3 33f 35v c ss1,2,3 0.1f 1000pf 1000pf* 10nf 1000pf* 10* 10pf 10* 2.2h 3.3h 6.8h 22pf c b1,2,3 0.1f sw1,2,3 d b1,2,3 m2 m1 m3 + 220f 4v + 220f 16v 3853 ta02 + 140k 1% 10* 10* 63.4k 1% 0.008 5% 10pf 0.011 5% *these filter components need to be close to the ic extv cc triple 1.8 v /1.2 v /2.5 v , 15 a high current step - down converter with r sense , f sw = 400khz tg1 tg2 boost1,2,3 sw1 sw2 bg1 bg2 sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1,2,3 v in intv cc drv cc12 ltc3853 mode/pllin 20k 1% freq/pllfltr ilim pgnd pgood12 sgnd extv cc tk/ss1,2,3 v fb3 sense3 ? sense3 + sw3 tg3 bg3 run1,2,3 pgood3 100* 100* 20k 1% 2.55k 10k 1% 4.7f 10k intv cc v out1 1.8v 15a v out2 1.2v 15a 20k 1% 0.002 5% v out3 2.5v 15a v in 6.5v to 14v c ith1,2,3 r ith1,2,3 1000pf* 660f 2.5v m1, m3, m5: rjk0305dpb m2, m4, m6: rjk0301dpb channel 1: r ith1 = 15k, c ith1 = 1500pf, c p1 = 330pf channel 2: r ith2 = 10k, c ith2 = 1500pf, c p2 = 220pf channel 3: r ith3 = 13k, c ith3 = 1500pf, c p3 = 330pf c p1,2,3 180f 16v c ss1,2,3 0.1f 1000pf 1000pf* 1000pf* 100* 100* 0.47h 0.56h 0.78h c b1,2,3 0.1f sw1,2,3 d b1,2,3 m3 m4 m1 m2 m5 m6 100* + 660f 2.5v 47pf + 660f 4v 3853 ta03 + 43.2k 1% 100* 24.9k 1% 0.002 5% 22pf 0.002 5% *these filter components need to be close to the ic ltc 3853 3853fc
33 for more information www.linear.com/ltc3853 typical applications dual 1.2 v /2.5 v high current step - down converter with r sense tg1 tg2 boost1,2,3 sw1 sw2 bg1 bg2 sense1 + extv cc sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1,2,3 v in intv cc drv cc12 ltc3853 mode/pllin 20k 1% freq/pllfltr ilim pgnd pgood12 sgnd tk/ss3 v fb3 sense3 ? sense3 + sw3 tg3 bg3 run1,3 pgood3 run2 100* 100* 2.55k 4.7f 10k intv cc v out1 1.2v 30a v out1 20k 1% 0.002 5% v out3 2.5v 15a v in 6.5v to 14v c ith1,3 r ith1,3 1000pf* 660f 2.5v 2 channel 1: r ith1 = 10k, c ith1 = 1500pf, c p1 = 220pf channel 2: i th1 and i th2 shorted together, tk/ss1 and tk/ss2 shorted together channel 3: r ith3 = 13k, c ith3 = 1500pf, c p3 = 330pf c p1,3 180f 16v c ss3 0.1f tk/ss1 c ss1 0.22f 1000pf 1000pf* 1000pf* 100* 200k 100* 0.47h 0.47h 0.78h c b1,2,3 0.1f sw1,2,3 d b1,2,3 100* + 660f 4v 3853 ta04 + 43.2k 1% 100* 10k 1% 0.002 5% 47pf 0.002 5% *these filter components need to be close to the ic ltc 3853 3853fc
34 for more information www.linear.com/ltc3853 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 40 39 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) ltc 3853 3853fc
35 for more information www.linear.com/ltc3853 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 12/10 change to operating temperature range updated order information part marking edits made to note 2 and 3 changes to graphs g01 and g02 updated related parts table 2 2 4 5 36 b 8/14 added h- and mp-grade parts 2, 3, 4, 7 c 3/15 corrected ic pin names added v out range corrected typographical errors 2 3 5, 21, 22 and 30 ltc 3853 3853fc
36 for more information www.linear.com/ltc3853 ? linear technology corporation 2008 lt 0315 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3853 related parts part number description comments ltc3850/ltc3850-1/ ltc3850-2 dual output synchronous step-down dc/dc controller r sense or dcr current sensing phase-lockable fixed 250khz to 780khz frequency, 4v v in 30v, 0.8v v out 5.25v ltc3861 dual output synchronous step-down dc/dc controller with diff amp, dcr current sense, polyphase ? and three-state output drive operates with power blocks, drmos devices or external mosfets 3v v in 24v ltc3855 dual output synchronous step-down dc/dc controller with diff amp, polyphase and dcr temperature compensation phase-lockable fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12v ltc3829 3-phase, single output synchronous step-down dc/dc controller with diff amp, polyphase and dcr temperature compensation phase-lockable fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.8v v out 5v ltc3856 2-phase, single output synchronous step-down dc/dc controller with diff amp, polyphase and dcr temperature compensation phase-lockable fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 5v ltc3851a/ ltc3851a-1 single output synchronous step-down dc/dc controller r sense or dcr current sensing phase-lockable fixed operating frequency 250khz to 750khz, 4v v in 38v, 0.8v v out 5.25v, msop-16e 3mm 3mm qfn-16, ssop-16 tg1 tg2 boost1,2,3 sw1 sw2 bg1 bg2 sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 v fb3 i th1 i th2 i th3 v in intv cc drv cc12 ltc3853 mode/pllin 20k 1% freq/pllfltr ilim pgnd pgood12 sgnd tk/ss1 sense3 ? sense3 + sw3 tg3 bg3 run1 run2 run3 pgood3 extv cc 100* 100* 2.55k 4.7f 10k intv cc v out1 2.5v 40a v out1 0.002 5% v out1 v in 6.5v to 14v c ith1 r ith1 1000pf* 660f 4v 3 r ith1 = 3.9k, c ith1 = 10nf, c p1 = 470pf 3 short tk/ss1, tk/ss2 and tk/ss3 together c p1 180f 16v c ss1 0.33f 1000pf 1000pf* 1000pf* 100* 100* 0.78h 0.78h 0.78h c b1,2,3 0.1f sw1,2,3 d b1,2,3 100* + 3853 ta05 100* 43.2k 1% 0.002 5% 47pf 0.002 5% *these filter components need to be close to the ic typical application three phase 2.5 v output high current step - down converter with r sense ltc 3853 3853fc

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